An Energy Aware Simplicial Processor for Embedded Morphological Visual Processing in Intelligent Internet-of-Things

M. VILLEMUR, P. JULIAN; ANDREAS G. ANDREOU

ELECTRONICS LETTERS

INST ENGINEERING TECHNOLOGY-IET

Año: 2018 p. 1 - 2

0013-5194

This letter presents the architecture implementation and testing of a SIMD processor for energy aware embedded morphological visual processing using the simplicial piece-wise linear approximation. The architecture comprises an array of 48 x 48 processing elements (PE), each connected to an eight neighbor clique operating on binary input and state data. The architecture is synthesized from a custom designed ultra low voltage CMOS library and fabricated in a 55nm CMOS technology. The chip is capable of dynamic voltage/frequency scaling with power supplies between 0.5 and 1.2 Volts. The fabricated chip achieves an overall performance of 293 TOPS/W with dynamic energy dissipation efficiency of 3.4fJ per OP at 0.6Volts.