Low Power 18-bit PWM with 41 ps Resolution in 130-nm CMOS

MORALES, JUAN I.; PAOLINI, EDUARDO E.; MANDOLESI, PABLO S.; CHIERCHIE, FERNANDO

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC

Lugar: New York; Año: 2021 p. 1 - 1

1549-7747

The design and evaluation of a new hybrid architecture for digital pulse-width modulation (DPWM) are presented in this paper. This scheme uses a counter-based module to obtain the coarse adjustment of the duty cycle and a pulse former with a delay-line approach for fine-tuning. The latter employs fewer delay stages than other schemes by using the propagation delay of the multi-bit tunable delay elements as part of the desired pulse width variation. Our delay element provides very good linearity with the capability to compensate for deviations in the digital-to-time conversion. The prototype fabricated in a standard 130-nm CMOS process has 18 bits resolution (an 8-bit counter combined with a 10-bit delay-line-based pulse former), and low-power consumption when it operates with switching frequencies from 100 kHz to 1 MHz and a clock frequency of 17 MHz. Comparison with other recent alternatives in the literature is also provided.